Stored program logic system using a common exchange circuit

ABSTRACT

A stored program logic system for use in a telephone central office of the space switching type connected to peripheral units includes: a data memory divided into areas, a computer assemblage with a program memory; and separate linking circuits connected to respective peripheral units. A common exchange circuit interconnects the data memory, the computer assemblage and the linking circuits.

CROSS-REFERENCE TO RELATED APPLICATIONS

This invention is a continuation-in-part application of Ser. No. 532,775of Dec. 16, 1974 and now abandoned, which in turn is a continuation ofapplication Ser. No. 444,975 of Feb. 22, 1974, now abandoned, which inturn is a continuation of application Ser. No. 324,794 of Jan. 18, 1973and now abandoned, which in turn is a continuation of application Ser.No. 190,043 of Oct. 18, 1971, now abandoned.

BACKGROUND OF THE INVENTION

The present invention relates to an electronic logic arrangement with astored program which can be used in private or public telephone centraloffices of the space switching type.

In a telephone central office having a memory with stored program andspace switching, the logic arrangement may monitor equipments, said tobe peripheral equipments, the function of which is to observe or modifythe condition of the electronic or electromechanical binary elementsused in telephony, such as, for example, relay contacts.

In present telephone central offices of the type described above, thefunction of the peripheral equipments is relatively reduced whereas mostof the data processing required for operating is ensured by a logicsystem with a stored program. This is why, among other things, thedrafting of programs is long and difficult. Programming is arduousbecause it has to include data about telephone operations, binaryinformation attributed to each type of peripheral equipment and alltransient or secondary data.

The logic system with stored program proposed in accordance with thisinvention overcomes these drawbacks by reducing the programming which nolonger includes the processing of transient or secondary data and whichprovides separate routines for telephone operations and binaryinformation attributed to each type of peripheral equipment.

The electronic logic with stored program contemplated by the presentinvention is essentially characterized by the fact that it combines:

A data memory divided into separate areas which can be linked to theperipheral equipments through linking circuits and through a commonexchange circuit; and

A program memory included in a computing assemblage and linked to thecommon exchange circuit through a test circuit and through theinput-output registers of the computing assemblage.

In accordance with other characteristics of the invention:

The computing assemblage preferably also comprises an instruction memorylinked to the latter by an addressing circuit which is also linked tothe test circuit; and wherein

The instruction memory preferably is also linked to an operating circuitwhich is linked to the said test circuit.

Other characteristics and advantages resulting from this invention willappear more clearly from the following detailed description taken inconjunction with the accompanying drawings in which:

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1 shows schematically, by way of example, one possible applicationof a logic arrangement according to this invention;

FIG. 2 shows the organization of the data memory and the common exchangecircuit;

FIG. 3 shows a common exchange logic circuit according to the invention;

FIG. 4 shows a linking circuit according to the invention;

FIG. 5 shows the organization of the computer; and

FIG. 6 is a flow chart of an example of operation of the logicarrangement according to the invention.

DESCRIPTION OF PREFERRED EMBODIMENT

In FIG. 1, the stored program logic includes a data memory 1 that islinked, via a common exchange circuit 2, first to a computer 3, and thenvia a number of linking circuits C1 . . . Cn, to peripheral equipmentsPla- Pnk . . . Pna- Pnk.

The common exchange circuit 2 sorts and checks the messages coming fromthe peripheral equipments Pla- Pnk, and writes them into the data memory1.

The following are examples of messages read from a peripheral equipmentvia a linking circuit and stored in the data memory: "The subscriber No.x has an off-hook condition," "There is a received digit," "Theconnection is established".

At the right time, the common exchange circuit 2 sends these processingorders to the computer 3 which processes them, using the programs storedin its memory. The result of these processing is orders created by thecomputer. These orders are temporarily stored in the data memory 1, thendistributed toward the peripheral equipments Pla- Pnk by the commonexchange circuit 2.

The following are several orders given to the peripheral equipment Pla-Pnk; "What is the state of the extension number y . . . ?", "Release theextension number z.", "Connect the junctor number p . . . to theoperator circuit number q . . . ", "Find a free local junctor".

The main peripheral equipments are the extension scanner which managesextensions, the route tester which manages the connection circuit, theauxiliary scanner which manages auxiliaries, that is to say operatorcircuits and digit receivers, and the junctor scanner which managesjunctors. Miscellaneous other peripheral equipments can be added forsupplementary facilities: Maintenance, metering, traffic supervision, .. .

FIG. 2 is a block diagram of the data memory 1 and the common exchangecircuit 2.

The data memory 1 is a conventional random access memory of any knowntype, such as for example a ferrite core memory or a semiconductor RAMhaving addressing means. It is divided into several identical areas 4 orfield. Each area 4 is composed of several rows of memory 1 and itscapacity is enough to store all the information that is required duringthe establishing of a call, such as for example the number of thedialing receiver used for that call, the number of calling party, thenumber of a peripheral equipment while it is connected to the logicarrangement, and so on.

An area 4 is associated with any call that is established by thetelephone exchange during the time it is being established. The computer3 and all the peripheral equipments Pnk can read in it the informationthey need for their operation, and write into it other information thatthey will need later. When the calling party is connected to the calledparty, it is not necessary to keep this information stored. So, the usedarea 4 is cleared i.e., all the bits in it become equal to zero. Thearea becomes free, and it can be chosen to be assigned to another call.

The common exchange circuit 2 includes a scanner 5, a conventionalbuffer register 6, a conventional address register 7, and a commonexchange logic circuit 8.

The scanner can be a binary counter which is sequentially stepped inresponse to pulses. When it does not receive any order, it addresses thefirst line of each area 4 successively. Each time it addresses a line,the information written in that line is transferred to the bufferregister 6 and the address of the line is written in the addressregister 7. In a preferred embodiment of the invention, the state (freeor not) of each area 4 is written in the last bits of the first line ofthe corresponding area. So, the state of the area 4 is transferred inthe last bits of the buffer register 6. As soon as the information istransferred from the first line of the area 4 to the buffer register 6,the common exchange logic circuit 8 reads the last bits of the bufferregister 6. Thus, it knows the state of the addressed area and it canchoose the following operation to be done.

For example, if the state of the area 4 is "area calling the computerfor a process," the common exchange logic circuit 8 sends the computer 3a signal informing it that it is needed. The computer 3 sends back asignal indicating whether it is free or not.

In a preferred embodiment of the invention, three wires in BUS connectthe common exchange circuit 2 to computer 3. On a first wire, there is asignal 1 or 0 according to whether the computer is busy or free. On asecond wire, there is a signal 1 or 0 according to whether the computeris faulty or not. On a third wire, there is a signal 1 or 0 according towhether the operation processed by the computer is finished or not; whenthe operation is finished, the computer is calling.

If the computer 3 is not free, that is to say it is processing anothercall, the scanner 5 under control of logic circuit 8 addresses the firstline of the following area 4. However, if the commputer is free, thebits in the buffer register 6 and the address register 7 are transferredinto the computer 3, then the common exchange logic circuit 8 modifiesthe state of the area 4. This state becomes "area waiting for an answerfrom the computer." Then, the common exchange logic circuit 8 orders thescanner to address each line of this area successively. Each time a lineis addressed, the bits in it are transferred into the buffer register 6first, and then into the computer 3. So while it processes a call, thecomputer 3 has all the information about the call at its disposal,stored in one of its own memories. Then, the scanner 5 addresses thefirst line of the following area 4, and its cycle goes on.

In a preferred embodiment of the invention, the area states are:

"area calling the computer for a process ordered by an extension scanner(or by another peripheral equipment),"

"area calling an auxiliary scanner (or another peripheral equipment) tosend it an order,"

"area waiting for an answer from the route tester number n (or anotherperipheral equipment),"

"area waiting for an answer from the computer",

"area free,"

"faulty area."

The common exchange circuit 2 can receive only one message at a time,coming from a peripheral equipment. If several linking circuits C1- Cnsimultaneously call the common exchange circuit 2, the latter mustchoose the call to be received. So, there are priority levels among theperipheral equipments. In a preferred embodiment of the invention, theauxiliary scanners have the highest priority, then the junctor scanners,the charge meters, the route testers, the maintenance and finally theextension scanners that have the lowest priority.

FIG. 3 shows a common exchange logic circuit 8 included into a commonexchange circuit 2.

The common exchange logic circuit 8 is a logic circuit which is designedin such a manner that it sends a signal to either the computer 3 or oneof the linking circuits C1- Cn, according to the value of the binaryelements received at the input of the common exchange logic circuit 8,said binary elements being the area state of the concerned area 4.Moreover, the common exchange logic circuit 8 is designed to sendorders, in the form of signals, to other elements such as scanner 5,buffer register 6 and address register 7 of the common exchange circuit2 when the computer 3 or a called linking circuit C1- Cn answers.

The common exchange logic circuit 8 includes a clock 9, a decoder 10,and a priority circuit 11. The clock 9 synchronizes every part of thedata memory 1 and of the common exchange circuit 2 by sending clocksignals to the scanner 5, the decoder 10, and the priority circuit 11.If several devices simultaneously call the data memory 1, the prioritycircuit 11 chooses the first call to be treated, according to apredetermined order. For example, one can choose that any call comingfrom the computer 3 has a higher priority than any call coming from alinking circuit C1- Cn.

The decoder 10 includes a register, into which the area state istransferred from the buffer register 6, and an electronic logic circuit.The electronic logic circuit is made of gates known per se, such as ANDgates or OR gates. These gates are arranged so that the logic circuitsends validation signals to blocks 3, 5, 6, 7, C1- Cn according to thesignals (end of operation, admitted, free circuit, . . . ) it receivesfrom computer 3, buffer register 6 and linking circuits C1- Cn, andaccording to the area state. Such a logic circuit will be apparent to aman skilled in the art. It is not described in detail here because theprecise circuit depends on the specific combinations of bits to bedecoded and depends on exchange characteristics, for example the numberof linking circuits, that is to say the number of types of peripheralequipments which are mounted in the exchange, or the number of thebinary elements chosen for writing the area state, and the code that ischosen for defining said area state.

In FIG. 4, the linking circuit Ci includes a linking circuit register12, an address register 13, and a linking logic circuit 14.

The linking circuit register 12 which can be a flip-flop array, isconnected to the buffer register 6 so that the bits written in thebuffer register 6 can be transferred into the linking circuit register12, and vice-versa. This connection is multiplied on each linkingcircuit register of each linking circuit C1- Cn, but only one linkingcircuit at a time receives a validation signal from the common exchangecircuit 2.

The validation signal is sent by the area state register in decoder 10included in the common exchange logic circuit 8. It is received by thelinking logic circuit 14 which controls the linking circuit register 12.In this manner, information transfer is possible between the bufferregister 6 and the linking circuit register 12 of only one linkingcircuit at a time.

In the same manner, the address register 13 is connected to the addressregister 7 of the common exchange circuit, so that an address written inone address register can be transferred into the other address register.This connection is multiplied on each address register of each linkingcircuit C1- Cn, but transferring an address is possible between theaddress register 7 and the address register 13 of only one linkingcircuit at a time, because the linking logic circuit 14 also controlsthe address register 13.

All the peripheral equipments Pil- Pik of a same type are connected tothe same linking circuit Ci. For example, all the extension scanners areconnected to the same linking circuit, so that there is only one linkingcircuit for all the extension scanners.

The linking circuit register 12 and the address register 13 areconnected to corresponding registers included in the peripheralequipments Pil- Pik. Thus, it is possible to transfer an informationfrom a line of the data memory 1 into a register of a peripheralequipment Pil- Pik via the buffer register 6 and the register 12 of thecorresponding linking circuit Ci, and vice-versa. The line of the datamemory 1 from which the information is transferred, or into which theinformation is written, respectively, is known. Effectively, its numberis written into the address register 7, and it is transferred into theaddress register of the peripheral equipment via the address register 13of the linking circuit.

One peripheral equipment processes only one communication at any onetime, corresponding to only one area. It stores the number of this areain one of its registers during the whole time it processes thecommunication. So that when it calls the data memory for sending itinformation at the end of the processing, it can send the number of thecorresponding area and address the data memory.

When the same peripheral equipment processes another communication, itwill store another area number.

The linking logic circuit 14 plays a part that is analogous to that ofthe common exchange logic circuit 8. Like it, it includes logic circuitsto send validation signals to the linking circuit register 12, to theaddress register 13, and either to one chosen peripheral equipment Pij,when it receives a validation signal from the common exchange logiccircuit 8 or to the common exchange logic circuit 8, when it receives acall signal from a peripheral equipment Pil- Pik. Moreover, it includesa priority circuit to choose which call must be treated first, whenseveral peripheral equipments, and eventually the common exchange logiccircuit 8, call it simultaneously.

In FIG. 5 the computer 3 includes a program memory 15, amacroinstruction library 16, an addressing block 17, an input-outputblock 18, a test block 19, and an operating block 20.

The program memory 15 is a random access memory of any known type, forexample a ferrite core memory. It contains all the information, programsand tables that are necessary for the running of the installation, andfor carrying out the telephone procedures, especially these which dependon the facilities and are particular to each PABX.

The macroinstruction library 16 is either a random access memory, or aprogrammable read only memory, of any known type, for example a ferritecore random access memory or a semiconductor programmable read onlymemory. It contains subroutines, especially these which are the same inall the PABXs of this type.

The addressing block 17 is composed of two parts: one for addressing theprogram memory 15, and the other for addressing the macroinstructionlibrary 16. The first part, which is for addressing the program memory17, includes: an address register 21 in which the address of theinstruction to be executed is stored, a jump register 22 in which iswritten the number to be added to the contents of the address register21 for obtaining the address of the following instruction to beexecuted, and an adding circuit 23 which adds the contents of theaddress register 21 and of the jump register 22, and sends the resultsto the address register 21. The second part, which is for addressing themacroinstruction library 16, includes: an address register 24 in whichthe address of the instruction to be executed is stored.

The information, whether program memory 15 or macroinstruction library16 is addressed, is stored in the operating block 20 which includes adecoder 34 and a register 33.

The input-output block 18 comprises an address register 25, an inputregister 26, an output register 27, and a logic unit 28. The computer 3is connected to any other part of the logic arrangement according to theinvention via this input-output block 18.

The input register 26 is an electronic register of any known type, withthe same capacity as an area 4 of the data memory 1. When the computer 3must carry out a process concerning a communication, the informationthat is stored in the area 4 attributed to this communication istransferred into the input register 26, via the buffer register 6 of thecommon exchange circuit 2. Previously, the address of this area 4 wastransferred from the address register 7 of the common exchange circuit 2into the address register 25 of the input-output block 18.

Then, the computer 3 carries out the process to be done, using theinformation stored in the input register 26 of the input-output block18. The way a process is carried out will be described more in detaillater. The result of a process makes it necessary to write supplementaryinformation into the concerned area 4, and to modify information thatwas previously inscribed. For this purpose, the computer 3 uses itsoutput register 27.

The output register 27 is a register of the same type as the inputregister 26 and has the same capacity. The computer 3 writes into itsoutput register 27 the new information, and the modified information, atthe place they must be written into the concerned area 4. Unchangedinformation is directly transferred from the input register 26 into theoutput register 27. So, when the process is finished, the contents ofthe output register 27 is exactly the new contents of the concerned area4.

The computer 3 then calls the common exchange circuit 2. The address ofthe concerned area 4 that remained in the address register 25 during thewhole process, is transferred into the address register 7 of the commonexchange circuit 2, and an order is given to scanner 5 for addressingthat area. Then, the information is transferred from the output register27 into the addressed concerned area 4, via the buffer register 6.

Transferring information from the common exchange circuit 2 into theinput-output block 18 and vice-versa, is controlled by the logic unit 28of block 18. The logic unit 28 comprises a clock and a priority circuit.The clock is a clock of any known type, which is controlled by the clockof the data-memory that operates with the computer 3, in order to run insynchronism therewith. It transmits sequential signals either toward thecommon exchange logic circuit 8, toward registers of the input-outputblock 18, or toward the test block 19. For example, such signals are:acknowledgement of a call from the common exchange circuit 2, actuationof the input register in order to make it possible to write (or totransfer) information into (from) it, end of writing, actuation of aregister of the test block 19 in order to make it possible to write into(to transfer from) it information coming from (to be written into) aregister of the input-output block 18, call of the common exchangecircuit 2, etc. The priority circuit is of any known type. It is neededwhen there are several common exchange circuits 2 mounted in parallel,each one being connected to a data memory 1, if eventually two or morecommon exchange circuits 2 call the computer 3 simultaneously. Thepriority circuit then chooses the common exchange circuit 2 which mustbe answered first.

When the common exchange circuit 2 calls the computer 3, it sends a callsignal to the logic unit 28. The clock of the logic unit 28 begins torun in synchronism with the clock of the common exchange logic circuit8. Then the logic unit 28 sends a signal to the common exchange logiccircuit 8 in order to indicate to it that the computer 3 is free. Then,information can be transferred from the data memory 1 to theinput-output block 18 via the common exchange circuit 2. First, theaddress of the concerned area 4 is transferred from the address register7 to the address register 25. The logic unit 28 sends validation signalsto the address register 25 and to the test block 19, so that the addressis transferred from the address register 25 to a register of the testblock 19. In block 19, the parity of the address is checked, and theresult is sent, as a signal, from test block 19 to the logic unit 28. Ifthe parity is faulty, the transfer of information is cancelled; if theparity is good, the transfer of information goes on.

When the operation is finished, the computer 3 calls the common exchangecircuit 2, that is to say the logic unit 28 sends a signal toward thecommon exchange logic unit 8. When the common exchange circuit 2 isfree, its common exchange logic circuit 8 sends an acknowledgementsignal to the logic unit 28. When receiving this signal, the logic unit28 sends a validation signal to the address register 25, then to theoutput register 27, in order their contents are transferred to thecommon exchange circuit 2.

The test circuit 19 includes two registers 29 and 30, a parity circuit31 and a comparison circuit 32.

The registers 29 and 30 have a capacity so that they can contain eithera word of the program memory 15 or a word of the data memory 1. Theregister 29 is a shift register. Its shifts are controlled bysubroutines written in the macroinstruction library 16. Thesesubroutines are transferred from the macroinstruction library 16 intothe operating block 20, where they are decoded to form shift ordersignals to be sent to register 29. There are shifts of register 29 whenonly a part of the information written in the register 29 is needed, forexample only a part of an instruction, if the contents of the register29 come from the program memory 15, or only a particular information, ifthe contents of the register 29 comes from the input register 26.

The parity circuit 31 is of any known type. It determines the parity bitof a binary information written in the register 29, and writes theparity bit into the register 30, while the contents of the register 29,except the parity bit, is transferred into the register 30. So, when theparity computing is finished, the information written in the register 30has an exact parity. The comparison circuit 32 is of any known type. Itcompares the information written in the registers 29 and 30, and somakes it possible to know whether their contents are the same or not. Inorder to check the parity of an information, the information is writteninto the register 29, its parity bit is computed in the parity circuit31, in the manner described above, then the contents of the registers 29and 30 are compared.

The operating block 20 includes a register 33 and a decoder 34. In theregister 33 is written the information whether program memory 15 ormacroinstruction library 16 is addressed. This information is writteninto the register 33 by the decoder 34. The decoder 34 receives programinstruction signals from the program memory 15 via the register 29, andsubroutine signals from the macroinstruction library 16. The decoder 34decodes these instructions and sends signals either to the register 29,or to the register 33 and to the jump register 22 or the addressregister 24, in order to control either shifts in the register 29 or toaddress the program memory 15 or the macroinstruction library 16.

The program memory 15 and the macroinstruction 16 interwork in thefollowing manner. The program memory 15 contains all the successiveprograms to be executed for carrying out a telephone procedure. Themacroinstruction library 16 includes subroutines which are selected fromthe programs recorded in the program memory 15. There is a type ofinstruction in the program memory 15 which is: "Call themacroinstruction number n".

Thus, while carrying out a program of program memory 15, if this type ofinstruction appears, the program in the program memory 15 is stopped,the n^(th) subroutine is executed in the macroinstruction library 16,then the program in the program memory 15 continues from the followinginstruction.

The role of some subroutines is to arrange the information in the datamemory and in the program memory. For arranging the information in thedata memory, there are subroutines which make the information pickedfrom input register 26 of the block 18, shifted in the register 29 ofthe test block 19, and placed at the right place in the output register27 of block 18. There are other subroutines which cause calculations tobe made in order to know the address of the instruction to be read inthe program memory.

FIG. 6 shows the flow diagram of an example of operation of the logicarrangement according to the invention. The chosen example is whathappens in the logic when a peripheral equipment calls it in order totransmit to it a number dialled by a user.

When the calling party lifted his handset, he heard the dial tone. So hedialled the number of the called party. We assume he has just dialledthe last digit of this number.

As soon as he lifted the handset, an area 4 of the data memory 1 waschosen for storing every information concerning the communication. Atthe moment he dials the last digit of the called number, the followinginformation is already recorded: "the area is waiting for a call from alinking circuit Ci," "a subscriber is dialing," so is the number of thedialing subscriber, the number of the digit receiver, and the digitsalready dialled by the subscriber.

The dialed digit is received and stored in a digit receiver. In step 35,the corresponding peripheral equipment Pij of this digit receiverobserves that a digit is received, then it calls the logic arrangement,that is to say it calls the corresponding linking circuit Ci, by sendinga call signal to the linking logic circuit 14 of the linking circuit Ci.

If there is no other call having a higher priority, the linking logiccircuit 14 sends an answer signal to the peripheral equipment Pij,allowing it to transfer information. So, the following information iswritten into the address register 13 and the linking circuit register12: the address of the concerned area in the data memory 1 (this addresswas already stored in a register of the peripheral equipment Pij), andthe information: "there is a received digit," the digit received, andthe number of the digit receiver.

The linking logic circuit 14 then sends a call signal to the decoder 10and the priority circuit 11 of the common exchange logic circuit 8included in the common exchange circuit 2. If there is no other callhaving a higher priority, the call from the linking circuit is decoded,and an answer signal, allowing the transfer of information is sent backfrom the decoder 10 to the linking logic circuit 14 of the linkingcircuit Ci.

The linking logic circuit 14 sends a read actuation signal to theaddress register 13. Simultaneously, the decoder 10 sends a writeactuation signal to the address register 7. As soon as these actuationsignals are received, the address is transferred. The decoder 10 thensends a signal to the scanner 5 for ordering it to stop the scanning ofthe data memory 1 and to directly address the area 4, the address ofwhich is written in address register 7. Simultaneously, it sends a writeactuation signal to the buffer register 6. The information written inthe first line of the addressed area is transferred into the bufferregister 6. The zone state of the area then is transferred into thedecoder 10. If the zone state is "the area is waiting for a call fromlinking circuit Ci," there is no mistake. So, the decoder 10 sends asignal to the linking logic circuit 14 of the linking circuit Ci.

The linking logic circuit 14 sends a read actuation signal to thelinking circuit register 12. Simultaneously, the decoder 10 sends awrite actuation signal to the buffer register 6. As soon as theseactuation signals are received, the information is transferred into thebuffer register 6. Then the buffer register 6 sends an acknowledgementsignal to the decoder 10. The decoder 10 sends a read actuation signalto the buffer register 6, and the information is transferred into thearea 4. The decoder 10 then writes into the buffer register 6 the newarea state: "the area is waiting for the computer to perform anoperation ordered by the linking circuit Ci" . The new area state istransferred into the first line of the addressed area 4. The decoder 10then sends a signal to the scanner 5 for ordering it to start again thescanning of the data memory 1.

In step 36, during the scanning of the data memory 1, the concerned area4 is addressed again, and its area state is written into the decoder 10.The buffer register 6 calls the priority circuit 11. If there is noother call having a higher priority, and if the computer 3 is free, thedecoder 10 sends a call signal to the computer 3. The call signal isreceived by the logic unit 28 of input-output block 18. As an answer,the logic unit 28 sends an acknowledgement signal to the decoder 10. Thedecoder 10 then sends a read actuation signal to the address register 7,at the same time that the logic unit 28 sends a write actuation signalto the address register 25. The address of the concerned area then istransferred from the address register 7 to the address register 25.

The address of the area includes a parity bit. So, the parity of theaddress is first checked. By sending actuation signals, the logic unit28 causes the parity of the address transferred from the addressregister 25 to the register 29 to be checked in the above described way,using the register 30, the parity circuit 31, and the comparison circuit32. In the normal case, the comparison circuit 32 sends the logic unit28 a signal to inform it that the parity is not faulty. The logic unit28 then sends a signal to the decoder 10.

The decoder 10 sends a read actuation signal to the buffer register 6,at the same time that the logic unit 28 sends a write actuation signalto the input register 26. The contents of the first line of theconcerned area 4, which were written in the buffer register 6, is thentransferred into the input register 26. The decoder 10 then modifies thearea state that is written in the last bits of the buffer register 6, bywriting in a coded way the new area state: "the area is waiting for ananswer from the computer".

The decoder 10 now sends a write actuation signal to the buffer register6, and a signal to the scanner 5 which then addresses the second line ofthe same area 4. The information so written in this second line istransferred into the buffer register 6. The decoder 10 sends a readactuation signal to the buffer register 6, at the same time that thelogic unit 28 sends a write actuation signal to the input register 26.So the contents of the second line of the concerned state 4 istransferred into the input register 26. The same operation is repeatedas many times as necessary, so that the contents of the whole area 4 iswritten into the input register 26.

In step 37, while every useful information is written in the inputregister 26, the logic unit 28 addresses the first line of the programmemory 15, via the test block 19 and the decoder 34 of the operatingblock 20. The instruction which is written in the first line of theprogram memory 15 is the first instruction of a program which isprovided for reading a table stored in the program memory 15. In thistable, every combination of the three following pieces of information isregistered: the state of the communication, the number of the callinglinking circuit, and information called "supplementary information".

In the chosen example, the state of the communication is "selection".The number of the calling linking circuit is the code number of thelinking circuit which is associated with the peripheral equipments whichobserve the dialing receivers. The supplementary information is: "adialing has been just received". These three main information units werewritten in the above mentioned area 4 of the data memory 1, and theywere transferred into the input register 26 of the input-output block18. When the reading of the table begins, the three main informationunits are transferred into the register 30 of the test block 19. Eachword of the table written in the program memory 15 is transferred intothe register 29 at the time it is read, and it is compared to thecontents of the register 30, by using the comparison circuit 32.

An information unit about the address of the program to be processed forcarrying out the telephone procedure is written in the table of theprogram memory 15 at a place that is associated to the correspondingcombination of the three main informations. So, each time the contentsof the registers 29 and 30 are compared, a signal is sent to the decoder34 to inform it of the result of the comparison. If the contents aredifferent, the decoder 34 writes into the register 33 that the programmemory 15 must be addressed again, and it writes "1 " in the jumpregister 22. The contents of the jump register 22 and of the addressregister 21 are added in the adding circuit 23, and the result of theaddition is written into the address register 21, so that the nextcombination in the table is addressed.

When the contents of the registers 29 and 30 are the same, theinformation about the address of the program to be processed is sent tothe decoder 34. The decoder 34 decodes this information, writes into theregister 33 that the program memory 15 must be addressed again, andwrites into the jump register 22 the number to be added to the addresspresently written in the address register 21 in order to obtain theaddress of the first instruction of the program to be processed. Theaddition is made in the adding circuit 23 and then the first instructionis read.

Each time an instruction is read, it is transferred into the register 29and a signal is sent to the decoder 34 to indicate whether the nextinstruction must be read, or whether a macroinstruction is called. Ifthe instruction must be read, the decoder 34 writes in the register 33that the program memory 15 must be addressed, and it writes "1" in thejump register 22. If a macroinstruction is called, the decoder 34 writesthe address of the concerned macroinstruction in the address register24, and writes in the register 33 that the macroinstruction library 16must be addressed.

Each time a macroinstruction is addressed, it is sent to the decoder 34.The decoder 34 carries out the orders included in the macroinstruction,generally shift orders to be applied to the register 29 for moving aninformation. Then the decoder 34 writes into the register 33 whether theprogram memory 15 or the macroinstruction library 16 must be addressed,and writes an address either into the jump register 22, or into theaddress register 24, according to the information included in the readmacroinstruction.

The result of the program is information about the next operation to becarried out. Each information unit is first written into the register29, moved to be placed at the right place in a line, then transferredinto the right line of the output register 27.

In the chosen example, the next operation to be carried out is finding afree junctor. The first information unit to be written in the outputregister 27 is the linking circuit to be called, that is to say the codenumber of the linking circuit associated with the junctor scanners. Thesecond information unit to be written in the output register 27 is the"supplementary information," that is to say the order to be given to thejunctor scanners: "Find a free junctor". In order to complete this"supplementary information" with the type of junctor to be chosen, thereis a subprogram included in the above mentioned program, for analysingthe called number. Thus, the called number is transferred from the inputregister 26 into the register 30 so that it can be compared withinformation included in the subprogram instructions. The type ofjunctor, that is to say whether it is a local connecting circuit or atrunk circuit, and the route it belongs to, are determined according tothe first digits of the called number. The type and the route of thejunctor are written into the output register 27 in the same manner asthe above mentioned informations.

The last instruction of the program sends a signal to the logic unit 28for informing it that the program is finished. Then the logic unit 28sends validation signals to the input register 26, to the outputregister 27, and to the test block 19, for transferring all theinformation that has not been changed from the input register 26 intothe output register 28 via the test block 19. The information that hasnot been changed is all the information that was written in the inputregister 26, except the number of the linking circuit and thesupplementary information. The information is put in the output register27 at the same place as it was written in the input register 26. So thecontents of the output register 27 is exactly the new contents of thearea 4.

In step 38, when the writing in the output register 27 is finished, thelogic unit 28 sends a call signal to the common exchange logic circuit 8of the common exchange circuit 2. The call signal is received by thedecoder 10 and the priority circuit 11. If there is no other call havinga higher priority, the priority circuit 11 sends a signal to the decoder10, and the call from the computer 3 is decoded. So the decoder 10 sendsa signal to the scanner 5 to stop the scanning of the data memory 1, andit sends back to the logic unit 28 an answer signal that allows thetransfer of information.

The logic unit 28 sends a read actuation signal to the address register25 of the input-output block 18. Simultaneously, the decoder 10 sends awrite actuation signal to the address register 7. As soon as theseactuation signals are received, the address is transferred. The decoder10 then sends a signal to the scanner 5 for ordering it to directlyaddress the first line of the area 4, the address of which is nowwritten in the address register 7.

The logic unit 28 sends a read actuation signal to the first line of theoutput register 27, at the same time that the decoder 10 sends a writeactuation signal to the buffer register 6. The contents of the firstline of the output register 27 is transferred into the buffer register6. Then the decoder 10 sends a write actuation signal to the bufferregister 6, and the contents of the latter is transferred into the firstline of the concerned area 4.

The decoder 10 then sends a signal to the scanner causing it to addressthe second line of the same area 4. The contents of the second line ofthe output register 27 is then transferred into the second line of thearea 4, via the buffer register 6, in the same way as described abovefor the first line. Then the whole contents of the output register 27 istransferred into the concerned area 4, line by line, in the same way. Assoon as the contents of the last line have been transferred, the decoder10 sends a signal to the scanner 5 for ordering it to start again thescanning of the data memory 1. The area state of the concerned area 4presently is "area calling a junctor scanner."

In step 39, during the scanning of the data memory 1, the concerned area4 is addressed again, and its area state is written into the decoder 10.The buffer register 6 calls the priority circuit 11. If there is noother call having a higher priority, the priority circuit 11 sends asignal to the decoder 10, and the latter calls the linking circuit Cjthat corresponds to the junctor scanners.

The call signal is received by the linking logic circuit 14 of thelinking circuit Cj. If the linking circuit Cj is free, that is to say ifthere is no other call having a higher priority, the linking logiccircuit 14 sends an acknowledgement signal to the decoder 10.

The decoder 10 sends a read actuation signal to the address register 7and to the buffer register 6 at the same time that the linking logiccircuit 14 sends a write actuation signal to the address register 13 andto the linking circuit register 12, respectively. So, the address of theconcerned area, and the contents of the first line of the area, aretransferred from the common exchange circuit 2 into the linking circuitCj.

The information to be transferred into the scanner junctor are theorder: "Find a free junctor" and the type and route of the junctor to befound. This information is written in a predetermined place in the area4, for example in the third line of the area 4. In such an example, allthe information to be transferred from the area 4 into a junctor scannerand vice-versa is always written in the third line of the area 4. So thecontents of the third line are transferred each time there is aninformation transfer between a junctor scanner and the logic unitaccording to the invention, in the following manner. As soon as theaddress and information is transferred into the registers of the linkingcircuit Cj, the linking logic circuit 14 sends to the decoder 10 anorder signal for addressing third line of the area 4. The decoder 10sends in turn to the scanner 5 an order signal for addressing the thirdline of the concerned area 4, and at the same time it sends a writeactuation signal to the buffer register 6. The contents of the thirdline of the area 4 is transferred into the buffer register 6. Then it istransferred into the linking circuit register 12 in the same way asdescribed above.

When all the useful information is written in the linking circuit Cj,the latter calls a junctor scanner. The call signal is received by alogic circuit included in the junctor scanner. If the junctor scanner isfree, its logic circuit sends back an acknowledgement signal. In theother case, it answers that it is not free, and the linking circuit Cjcalls another junctor scanner, and so on until a junctor scanner answersit is free.

Then the information is transferred from the linking circuit Cj into thefree junctor scanner, line by line, in a way that is analogous to theabove described ways. As soon as the transfer is finished, the junctorscanner begins to execute the order.

What is claimed is:
 1. A stored program logic system for use with aplurality of peripheral equipments comprising: a data memory (1) havinga plurality of addressed fields (4) for storing processable data, acommon exchange means including scanning means (5) for selecting fieldsof said data memory, an exchange address register (7) for storing theaddress of the field to be selected by said scanning means, an exchangebuffer register (6) connected to said data memory for receiving datafrom or transferring data to said data memory and exchange control (8)means for controlling the reception and transmission of addresses anddata by said register; a linking means for interfacing the peripheralequipments with said common exchange means including a linking addressregister (13) connected to said exchange address register for receivingand storing an address therefrom or transferring thereto an addressstored in said linking address register, a linking circuit register (12)connected to said exchange buffer register for receiving and storingdata therefrom and for transferring thereto data stored in said linkingcircuit register, said linking circuit register being connectable toperipheral equipments for receiving data therefrom and transferring datathereto, and linking control means (14) for controlling the transmissionand reception of addresses and data by said registers; and a computer,said computer comprising means for processing data (15, 16, 17, 19), acomputer address register means (25) connected to said exchange addressregister for receiving and storing addresses therefrom and transferringthereto addresses stored in said exchange address register, computerbuffer register means (26, 27) for receiving data from and transferringdata to said exchange buffer register, and computer control means forcontrolling the transmission and reception of addresses and data by saidregister means.